DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER (20150250)
Authors :
MISS. RUTUJA ABHANGRAO
, MISS. SHILPA JADHAV,
, MISS PRIYANKA GHODKE, PROF. ALTAAF MULANI
Abstracts : Todays technology has raised demand for fast and real
time signal processing operation. Multiplication is one
of the most important arithmetic operations. In this
paper, we have proposed design of vedic multiplier
using Urdhva Tiryagbhyam sutra in Xilinx ISE. This
design takes lesser time for operation than currently
available multipliers .It encompasses wide era of
image processing and digital signal processing in much
efficient way with increase in speed and thus leading
to higher performance rating
Pages : 24-26
Downloads : 194
Publication Date : 2017-03-26
Modified Date : 2018-01-18
Cite/Export
MISS. RUTUJA ABHANGRAO ,
MISS. SHILPA JADHAV, ,
MISS PRIYANKA GHODKE, PROF. ALTAAF MULANI ,
"DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER", JournalNX - A Multidisciplinary Peer Reviewed Journal, NCMTEE-2K17, ISSN : 2581-4230, Page No. 24-26