Volume 2, Issue 12

FPGA IMPLEMENTATION OF 16 BIT RISC CPU AND PERFORMANCE ANALYSIS (20150137)

DOI :
Authors :
Abstracts : RISC (Reduced Instruction Set Computer) found several application in the engineering. In this paper, authors have design, implement and performance analysis of a 16-bit Reduced Instruction Set (RISC) CPU using XILINX tool. The significant attribute of the RISC processor is that it is incredibly simple and sustains load/store architecture. The processor includes the ALU, Shifter, Register array, Instruction register, program counter, address register, Operand register, Comparator and Control unit. The performance parameters like area and propagation interruption are analyzed at 90 nm process tools using SPARTAN 3- XC3S400 FPGA and XILINX tool.
Pages : 21-24
Downloads : 105
Publication Date :
Modified Date : 2018-01-16
Cite/Export
DINESH B BORUDE , PROF.S.V.VERMA , "FPGA IMPLEMENTATION OF 16 BIT RISC CPU AND PERFORMANCE ANALYSIS", JournalNX - A Multidisciplinary Peer Reviewed Journal, Volume 2, Issue 12, ISSN : 2581-4230, Page No. 21-24
Peer reviewed